1. Technical Field
The present disclosure relates generally to semiconductor processing, and, more particularly, to manufacturing a trench capacitor for high voltage processes.
2. Description of the Related Art
A simple capacitor consists of two conducting plates separated by dielectric material. Ions and electrons in the dielectric material migrate to opposite plates and form an electric field within the dielectric material when a voltage is applied across the two conducting plates. The charge separation and the electric field are maintained when the voltage is removed so that the capacitor can store energy equivalent to the work required to form the electric fields by moving the ions and electrons. Capacitors are used in a wide variety of semiconductor devices and a variety of techniques have been developed to form capacitors.
FIGS. 1A, 1B, and 1C conceptually illustrate a conventional technique for forming a capacitor using bipolar technology. An SOI substrate 105 is used as the starting material for forming the capacitor. As depicted in FIG. 1A, the SOI substrate 105 is comprised of a bulk substrate 110, a buried insulation layer 115 and an active layer 120. Typically the bulk substrate 110 is comprised of silicon, the buried insulation layer 115 is comprised of silicon dioxide (a so-called “BOX” layer), and the active layer 120 is comprised of silicon (doped or undoped). Such SOI structures may be readily obtained from a variety of commercially known sources. Typically, the buried insulation layer 115 will be relatively thick, e.g., on the order of approximately 0.5-2 microns, and the active layer 120 may have an initial thickness of approximately 1-5 microns.
The active layer 120 is a layer of epitaxial silicon that is deposited in an epi reactor. The active layer 120 is doped with an N-type dopant material, e.g., phosphorous or arsenic. Note that the distribution of dopant atoms within the active layer 120 may not be uniform throughout its depth. An epitaxial layer 125 of silicon is then grown over the active layer 120. Growing the epitaxial layer 125 (which is also referred to as an N-epi region or a P-epi region for a capacitor formed using the opposite dopants) also causes some of the dopant material to diffuse out of the active layer 120 and form a buried layer 130 (which may also include some or all of the active layer 120). Although FIG. 1A depicts the layers 120, 125, 130 as distinct layers, in practice the boundaries between the layers 120, 125, 130 may be very difficult to define. Nevertheless, the distinct layers are shown for purposes of explanation only. The dopant concentration varies from a relatively high level in the layer 120 to a relatively low level in the layer 125. The dopant concentration in the buried doped layer 130 is typically in the range of approximately 1018-20 atoms/cm−3 and the dopant concentration in the N-epi region 125 is typically in the range of approximately 1014-16 atoms/cm−3.
FIG. 1B shows the formation of illustrative sinkers 135. The sinkers 135 are formed by implanting an N-type dopant material and then applying heat to cause the dopant material to diffuse outwards and downwards so that the sinkers 135 overlap with the buried layer 130. The region in which the sinkers 135 overlap (or crossover) with the buried layer 130 is typically referred to as the crossover region 137. The dopant concentration in the crossover region 137 is approximately in the range from 2×1015 to 5×1017 ions/cm3. The dopant concentration in other portions of the buried layer 130 and/or the sinkers 135 is typically higher than the dopant concentration in the crossover region. The dopant concentration is typically lower for thicker epi layers 125 because it is harder to diffuse down from the sinker 135 and up from the buried layer 130.
FIG. 1C shows a trench 140 that is formed between the sinkers 135. The trench 140 includes a dielectric portion 145 and a polysilicon fill 150. For example, the buried layer 130 and the N-epi region 125 may be etched to form the trench 140 and then a dielectric (or stack of dielectrics) can be deposited on the walls of the trench 140. The poly fill 150, which may be doped or undoped, is used to fill the remaining opening in the trench 140. The polysilicon fill 150 forms one of the “plates” of the capacitor and the doped regions 130, 135 form the other “plate” of the capacitor. The dielectric portion 145 forms the “dielectric” of the capacitor. Applying voltages to the contacts (C+, C−) of the capacitor causes ions and electrons in the dielectric portion 145 to migrate towards the doped regions 130, 135 and the polysilicon fill 150. Although not shown in FIG. 1C, the capacitor may also include various passivation layers and contacts.
FIG. 2 shows the variation in capacitance of the capacitor depicted in FIG. 1C as a function of the applied voltage. The horizontal axis indicates the applied bias voltage and the vertical axis indicates the normalized capacitance (C_norm). The normalized capacitance is the measured capacitance of the capacitor divided by its ideal capacitance, which in this case is the accumulation region capacitance. The capacitor depicted in FIG. 1C is prone to deep depletion effects during pulsing and/or sweeping of the bias voltage from accumulation to inversion. The inset figure shows an applied bias voltage that begins at +40 V, steps down to −40 V, and then ramps back up to +40 V with increasing time. When this voltage profile is applied to the capacitor shown in FIG. 1C, the normalized capacitance drops to less than 0.92 when the applied bias voltage drops from +40V to −40V. The normalized capacitance then rises with increasing bias voltage until it reaches approximately 1.0 at a bias voltage of approximately +10V. The depletion effects exhibited at large negative biasing voltages are believed to be, at least in part, a consequence of the thickness of the dielectric region 145 and the effect of lateral and/or crossover diffusion of dopants in the doped regions 130, 135.